A 4.5 ns access time 1K x 4 bit ECL RAM
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (5) , 515-520
- https://doi.org/10.1109/jssc.1983.1051986
Abstract
An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT.Keywords
This publication has 3 references indexed in Scilit:
- A 3-ns 1-kbit RAM using super self-aligned process technologyIEEE Journal of Solid-State Circuits, 1981
- A 6ns 4Kb bipolar RAM using switched load resistor memory cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- An advanced PSA process for high speed bipolar VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979