A 12 MHz data cycle 4 Mb DRAM with pipeline operation
- 1 April 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (4) , 479-483
- https://doi.org/10.1109/4.75042
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- A high random-access-data-rate 4 Mb DRAM with pipeline operationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- New nibbled-page architecture for high-density DRAMsIEEE Journal of Solid-State Circuits, 1989
- The design and performance of CMOS 256K bit DRAM devicesIEEE Journal of Solid-State Circuits, 1984
- A 64K DRAM with 35 ns static column operationIEEE Journal of Solid-State Circuits, 1983
- A 100ns 64K dynamic RAM using redundancy techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981