Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Top Cited Papers
- 29 April 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 91 (2) , 305-327
- https://doi.org/10.1109/jproc.2002.808156
Abstract
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.Keywords
This publication has 45 references indexed in Scilit:
- High-performance and low-power challenges for sub-70 nm microprocessor circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pipeline gating: speculation control for energy reductionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- V/sub TH/-hopping scheme to reduce subthreshold leakage for low-power processorsIEEE Journal of Solid-State Circuits, 2002
- DRG-cache: a data retention gated-ground cache for low powerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Circuit-level techniques to control gate leakage for sub-100 nm CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A dynamic voltage scaled microprocessor systemIEEE Journal of Solid-State Circuits, 2000
- A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage schemeIEEE Journal of Solid-State Circuits, 1998