Design for reliability, testability and manufacturability of memory chips
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 22 references indexed in Scilit:
- The nature of defect size distributions in semiconductor processesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A variable-stress shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Defect size distribution in VLSI chipsIEEE Transactions on Semiconductor Manufacturing, 1991
- A high performance 16-Mb DRAM technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Yield modeling from SRAM failure analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Fact and fiction in yield modelingMicroelectronics Journal, 1989
- Analysis and reduction of sense-amplifier offsetIEEE Journal of Solid-State Circuits, 1989
- Optimized sensing scheme of DRAMsIEEE Journal of Solid-State Circuits, 1989
- Critical area and critical levels calculation in IC yield modelingIEEE Transactions on Electron Devices, 1988
- Integrated circuit yield statisticsProceedings of the IEEE, 1983