Test generation and verification for highly sequential circuits
- 1 May 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 10 (5) , 652-667
- https://doi.org/10.1109/43.79502
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CONTEST: a concurrent test generator for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Approaches to multi-level sequential logic synthesisPublished by Association for Computing Machinery (ACM) ,1989
- Logic verification algorithms and their parallel implementationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- On the verification of sequential machines at differing levels of abstractionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Verification algorithms for VLSI synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Test generation for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Test generation by activation and defect-drive (TEGAD)Integration, 1985