Mechanical Stress in VLSI Interconnections: Origins, Effects, Measurement, and Modeling

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Abstract
Problems with mechanical stress in very large-scale integration (VLSI) interconnections appeared quite early in the history of the industry. Failures were observed in the dielectric itself, in the die, and in metal lines. Various process and design changes were made to fix the problems, but the continuing shrinking of dimensions and increased complexity of interconnection structures have resulted in recurrence of old problems, the appearance of new ones, and increasing difficulty in developing fixes. The choices for interconnection materials and processes have become increasingly constrained. The shift from hermetic to plastic packaging reduces the choices for passivation materials. The reduced dimensions for the active devices and the corresponding shortening of diffusion distances limit the “thermal budget”; interconnection processing must be carried out quickly and at relatively low temperatures. The reduced space available for interconnections has resulted in the use of high aspect ratios, multiple layers of metal, and the need for planarization. These all lead to further constraints on materials and processes. An additional complicating factor is the continuing effort to reduce the time from initial design to marketing the product. Since many mechanical-stress-induced problems are wear-out reliability problems, they may require extensive testing for detection. If a problem is not found until late in the product cycle, the economic consequences may be severe. To avoid costly late detection of problems and frantic scrambles for fixes, it is essential to have a clear understanding of the various origins of mechanical stress, the behavior of various materials and interfaces under stress, and the potential failure mechanisms.