Scaling Limits of Silicon VLSI Technology

This publication has 16 references indexed in Scilit:

• SOLID-II: High-voltage high-gain kilo-Ångstrom-channel-length CMOSFET's using Silicide with self-aligned ultrashallow (3S) junction
  IEEE Transactions on Electron Devices, 1986
• A fully scaled submicrometer NMOS technology using direct-write E-beam lithography
  IEEE Transactions on Electron Devices, 1985
• A new tungsten gate process for VLSI applications
  IEEE Transactions on Electron Devices, 1984
• TaSi 2 gate for VLSI CMOS circuits
  IEEE Transactions on Electron Devices, 1984
• Generalized scaling theory and its application to a ¼ micrometer MOSFET design
  IEEE Transactions on Electron Devices, 1984
• Spatial distribution of hot electrons as a physical limit to MOS transistor performance
  Electronics Letters, 1982
• Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor
  IEEE Transactions on Electron Devices, 1980
• 1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications
  IEEE Journal of Solid-State Circuits, 1979
• Design of ion-implanted MOSFET's with very small physical dimensions
  IEEE Journal of Solid-State Circuits, 1974
• Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit
  Physical Review B, 1967