On achieving complete fault coverage for sequential machines
- 1 March 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (3) , 378-386
- https://doi.org/10.1109/43.265679
Abstract
A method for generating tests for gate-level stuck-at faults in sequential machines is given, which is applicable when a state-table description of the machine under test is either given or extractable from the given description. A test generation procedure for faults in the state table is first described. The test generation procedure is polynomial in the size of the state table, and is complete and accurate in the following sense. For every given state-table fault, the procedure provides either a minimum-length test, or a proof that the fault is undetectable. This test generation procedure is used for generating complete test sets for stuck-at faults in a gate level implementation of the machine, by translating stuck-at faults in the gate-level implementation into faults in the state table. The translation includes modeling and extraction. Modeling consists of a simple method to select a small subset of state-table faults such that a test set for these faults yields very high coverage of stuck-at faults in the actual implementation. Extraction consists of accurate translation of stuck-at faults in the implementation into equivalent state-table faults, and can be used to derive tests for stuck-at faults which are not detected by the test set for the modeled faults. Based on the test generation algorithm developed and the modeling and extraction of stuck-at faults to translate them into state-table faults, a method to achieve 100% fault-efficiency for stuck-at faults is proposed, and experimental results for stuck-at faults are presented. Short test sequences are shown to be obtainedKeywords
This publication has 21 references indexed in Scilit:
- A protocol test generation procedurePublished by Elsevier ,2003
- On properties of algebraic transformation and the multifault testability of multilevel logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test generation for synchronous sequential circuits using multiple observation timesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On achieving complete fault coverage for sequential machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Test generation and verification for highly sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- On achieving a complete fault coverage for sequential machines using the transition fault modelPublished by Association for Computing Machinery (ACM) ,1991
- A functional-level test generation methodology using two-level representationsPublished by Association for Computing Machinery (ACM) ,1989
- Test pattern generation for sequential MOS circuits by symbolic fault simulationPublished by Association for Computing Machinery (ACM) ,1989
- Test generation for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987