A 1-Gb/s, four-state, sliding block Viterbi decoder
- 1 June 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (6) , 797-805
- https://doi.org/10.1109/4.585246
Abstract
No abstract availableThis publication has 15 references indexed in Scilit:
- Algorithms and architectures for concurrent Viterbi decodingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- A 140-Mb/s, 32-state, radix-4 Viterbi decoderIEEE Journal of Solid-State Circuits, 1992
- Survivor sequence memory management in Viterbi decodersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- High-speed CMOS circuit techniqueIEEE Journal of Solid-State Circuits, 1989
- An alternative to metric rescaling in Viterbi decodersIEEE Transactions on Communications, 1989
- Convolutional Code Structure and Viterbi DecodingPublished by Springer Nature ,1981
- A 50 Mbit/s Multiplexed Coding System for Shuttle CommunicationsIEEE Transactions on Communications, 1978
- The viterbi algorithmProceedings of the IEEE, 1973
- Viterbi Decoding for Satellite and Space CommunicationIEEE Transactions on Communication Technology, 1971