State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs

Abstract
This is a review paper that discusses the state-of-the-art issues for electrostatic discharge (ESD) protection devices. The important device physics of the protection devices, the device phenomena under high-current ESD events, the effects of process technology and advanced scaling effects are discussed. Some description of the advanced protection scheme designs and their performance for the various ESD stress models are presented. The main focus of the paper is on the impact of technology on ESD design and the critical issues facing the ability to achieve good ESD reliability as the technologies advance into the deep sub-micron regimes.

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