A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Clock dithering for electromagnetic compliance using spread spectrum phase modulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A portable digital DLL architecture for CMOS interface circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLLIEEE Journal of Solid-State Circuits, 1997
- A semidigital dual delay-locked loopIEEE Journal of Solid-State Circuits, 1997
- A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architectureIEEE Journal of Solid-State Circuits, 1996
- Multifrequency zero-jitter delay-locked loopIEEE Journal of Solid-State Circuits, 1994