Suppression of the boron penetration induced Si/SiO/sub 2/ interface degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET
- 1 May 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 15 (5) , 160-162
- https://doi.org/10.1109/55.291600
Abstract
The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO/sub 2/ interface. An atomically flat Si/SiO/sub 2/ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p/sup +/ poly-Si gate MOS devices even with the annealing temperature as high as 1000/spl deg/C.Keywords
This publication has 7 references indexed in Scilit:
- The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Characterization of ultrathin oxide prepared by low-temperature wafer loading and nitrogen preannealing before oxidationJournal of Applied Physics, 1992
- High-performance polysilicon contacted shallow junctions formed by stacked-amorphous-silicon filmsIEEE Electron Device Letters, 1992
- Fluorine diffusion on a polysilicon grain boundary network in relation to boron penetration from P/sup +/ gatesIEEE Electron Device Letters, 1992
- A comprehensive study on p/sup +/ polysilicon-gate MOSFET's instability with fluorine incorporationIEEE Transactions on Electron Devices, 1990
- Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technologyIEEE Electron Device Letters, 1989
- Design tradeoffs between surface and buried-channel FET'sIEEE Transactions on Electron Devices, 1985