A low overhead design for testability and test generation technique for core-based systems-on-a-chip

This publication has 25 references indexed in Scilit:

• Hierarchical Test Generation And Design For Testability Of ASPPs and ASIPs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Concurrent analysis techniques for data path timing optimization
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• HITEC: a test generation package for sequential circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• PROOFS: a fast, memory efficient sequential circuit fault simulator
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• A design-for-testability technique for register-transfer level circuits using control/data flow extraction
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
• Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997
• Synthesis of application specific instruction sets
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
• Test generation for data-path logic: the F-path method
  IEEE Journal of Solid-State Circuits, 1988