A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM
- 1 October 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (5) , 1233-1237
- https://doi.org/10.1109/jssc.1989.572586
Abstract
A 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power dissipation has been achieved using new circuit techniques: a grounded-gate, nonlatching-type level converter with a wired-OR predecoder and a direct column sensing scheme having a cascode differential amplifier. As a result of extensive use of high-speed bipolar ECL circuits with self-aligned bipolar transistors, the RAM attains high-speed performance without degrading the low-power BiCMOS RAM characteristics.Keywords
This publication has 9 references indexed in Scilit:
- An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array sizePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An 8 ns 1 Mb ECL BiCMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 9 ns 1 Mb CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 12-ns ECL I/O 256 K*1-bit SRAM using a 1- mu m BiCMOS technologyIEEE Journal of Solid-State Circuits, 1988
- A 4-ns 4K*1-bit two-port BiCMOS SRAMIEEE Journal of Solid-State Circuits, 1988
- An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capabilityIEEE Journal of Solid-State Circuits, 1988
- An 8ns 256k Bicmos RamPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A 7-ns/350-mW 64-kbit ECL-compatible RAMIEEE Journal of Solid-State Circuits, 1987
- Hot-carrier generation in submicrometer VLSI environmentIEEE Journal of Solid-State Circuits, 1986