Address equation multiplexing for real-time signal processing applications
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes several sharing techniques, tuned to hardware address generation for large memories in real-time signal processing systems. These strategies are oriented to minimize the area overhead introduced by the use of application-specific address generation units. The objective is to explore at the system level, when the signal processing application is being defined, the trade-offs involved in alternative algorithmic specifications. This will allow one to arrive faster at area efficient specifications as input for the actual address hardware generation stage. The principles are demonstrated on a realistic test-vehicle for which very promising results have been achieved.Keywords
This publication has 8 references indexed in Scilit:
- Synthesis of address generatorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Heuristic techniques for the synthesis of complex functional unitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An algorithm for array variable clusteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimization of address generator hardwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Address generation for array access based on modulus m countersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- PHIDEO: a silicon compiler for high speed algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-Level Synthesis for Real-Time Digital Signal ProcessingPublished by Springer Nature ,1993
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992