An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
- 1 January 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the capacity of shared last-level caches efficiently and to allow for a short access time, proposed non-uniform cache architectures (NUCAs) are organized into per-core partitions. If a core runs out of cache space, blocks are typically relocated to nearby partitions, thus managing the cache as a shared cache. This uncontrolled sharing of all resources may unfortunately result in pollution that degrades performance. We propose a novel non-uniform cache architecture in which the amount of cache space that can be shared among the cores is controlled dynamically. The adaptive scheme estimates, continuously, the effect of increasing/decreasing the shared partition size on the overall performance. We show that our scheme outperforms a private and shared cache organization as well as a hybrid NUCA organization in which blocks in a local partition can spill over to neighbor core partitionsKeywords
This publication has 8 references indexed in Scilit:
- A Case for MLP-Aware Cache ReplacementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Managing Wire Delay in Large Chip-Multiprocessor CachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip MultiprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Optimizing Replication, Communication, and Capacity Allocation in CMPsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Fair cache sharing and partitioning in a chip multiprocessor architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Distance associativity for high-performance energy-efficient non-uniform cache architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- SimpleScalar: an infrastructure for computer system modelingComputer, 2002
- Characterizing computer performance with a single numberCommunications of the ACM, 1988