DIBL in short-channel NMOS devices at 77 K
- 1 April 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 39 (4) , 908-915
- https://doi.org/10.1109/16.127482
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 KSolid-State Electronics, 1990
- Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devicesIEEE Transactions on Electron Devices, 1990
- Cryogenic operation of CMOS-based microsystems and computersMicroprocessors and Microsystems, 1989
- MOS device modeling at 77 KIEEE Transactions on Electron Devices, 1989
- Computer-Aided Design and VLSI Device DevelopmentPublished by Springer Nature ,1988
- Submicrometer-channel CMOS for low-temperature operationIEEE Transactions on Electron Devices, 1987
- Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistanceSolid-State Electronics, 1986
- Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulationsIEEE Transactions on Electron Devices, 1986
- Short-channel effects in MOSFET's at liquid-Nitrogen temperatureIEEE Transactions on Electron Devices, 1986
- VLSI limitations from drain-induced barrier loweringIEEE Transactions on Electron Devices, 1979