The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K
- 31 October 1990
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 33 (10) , 1265-1273
- https://doi.org/10.1016/0038-1101(90)90029-e
Abstract
No abstract availableKeywords
This publication has 17 references indexed in Scilit:
- Cryogenic operation of CMOS-based microsystems and computersMicroprocessors and Microsystems, 1989
- Digital characteristics of CMOS devices at cryogenic temperaturesIEEE Journal of Solid-State Circuits, 1989
- Operational characteristics of CMOS op-amps at cryogenic temperaturesSolid-State Electronics, 1988
- Submicrometer-channel CMOS for low-temperature operationIEEE Transactions on Electron Devices, 1987
- Short-channel effects in MOSFET's at liquid-Nitrogen temperatureIEEE Transactions on Electron Devices, 1986
- Miniaturization of Si MOSFET's at 77 KIEEE Transactions on Electron Devices, 1982
- VLSI limitations from drain-induced barrier loweringIEEE Transactions on Electron Devices, 1979
- Subthreshold conduction in MOSFET'sIEEE Transactions on Electron Devices, 1978
- Very small MOSFET's for low-temperature operationIEEE Transactions on Electron Devices, 1977
- Subthreshold design considerations for insulated gate field-effect transistorsIEEE Journal of Solid-State Circuits, 1974