Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits
- 1 December 1994
- journal article
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 41 (6) , 2229-2234
- https://doi.org/10.1109/23.340567
Abstract
Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach.<>Keywords
This publication has 5 references indexed in Scilit:
- Design And Testing Of SEU/ SEL Immune Memory And Logic Circuits In A Commercial Cmos ProcessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Low power SEU immune CMOS memory circuitsIEEE Transactions on Nuclear Science, 1992
- SEU hardened memory cells for a CCSDS Reed-Solomon encoderIEEE Transactions on Nuclear Science, 1991
- An SEU-hardened CMOS data latch designIEEE Transactions on Nuclear Science, 1988
- An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAMIEEE Transactions on Nuclear Science, 1987