An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM
- 1 January 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 34 (6) , 1281-1286
- https://doi.org/10.1109/tns.1987.4337466
Abstract
A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling resistors in the LRAM are used only to protect against the short n-channel transient; longer persisting pulses are reduced in magnitude by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.3 nsec were measured for transients following strikes at the n- and p-channel drains, respectively--primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Test structures of the new design exhibit equivalent SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM.Keywords
This publication has 11 references indexed in Scilit:
- Single Event Upset In CMOS Static Ram And LatchesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- RAM cell recovery mechanisms following high-energy ion strikesIEEE Electron Device Letters, 1987
- An Approach to Measure Ultrafast-Funneling-Current TransientsIEEE Transactions on Nuclear Science, 1986
- An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMSIEEE Transactions on Nuclear Science, 1986
- Numerical Simulation of SEU Induced Latch-UpIEEE Transactions on Nuclear Science, 1986
- Memory SEU simulations using 2-D transport calculationsIEEE Electron Device Letters, 1985
- Comparison of 2D Memory SEU Transport Simulation with ExperimentsIEEE Transactions on Nuclear Science, 1985
- Comparison of Analytical Models and Experimental Results for Single Event Upset in CMOS SRAMsIEEE Transactions on Nuclear Science, 1983
- Charge Funneling in N- and P-Type Si SubstratesIEEE Transactions on Nuclear Science, 1982
- Auger coefficients for highly doped and highly excited siliconApplied Physics Letters, 1977