A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz
- 1 April 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (4) , 513-519
- https://doi.org/10.1109/4.753684
Abstract
No abstract availableKeywords
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