A new tool for random testability evaluation using simulation and formal proof

1 January 1992

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 321-326
https://doi.org/10.1109/vtest.1992.232773

Abstract

NUMBER OF PAGES: xiv+344A set of tools is described, allowing one to compute random testability measurement for combinational circuits, based on a black box worst case hypothesis. These tools provide enough information to allow circuit modification, in order to meet a prescribed testability value. The efficiency of these tools is due to the use of a statistical method combined with formal proof mechanisms. The random testability of the complete ISCAS benchmark of combinational circuits is computed. For the least testable circuits, a few modifications, guided by the testability measurements, are shown to be sufficient to make them randomly testable

Keywords

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