Finding defects with fault models
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 498-505
- https://doi.org/10.1109/test.1995.529877
Abstract
A process is presented to validate fault models used in fault diagnosis. Known defects are inserted, using a focused ion beam (FIB), into production ICs and their behavior is compared to that predicted in fault simulation. The fault model is refined until it matches the observed defect behavior. The process is then repeated with known defects in unknown ("blind") locations, and necessary modifications to the model are again made. Finally, the model is used to diagnose chips with unknown defects. Experimental results on several chips demonstrate the value of the approach, which can be extended to test pattern generation and test quality estimation as well as fault diagnosis.Keywords
This publication has 20 references indexed in Scilit:
- "RESISTIVE SHORTS" WITHIN CMOS GATESPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Carafe: an inductive fault analysis tool for CMOS VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholdsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Defect classes-an overdue paradigm for CMOS IC testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Diagnosing CMOS bridging faults with stuck-at fault dictionariesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Accurate and efficient fault simulation of realistic CMOS network breaksPublished by Association for Computing Machinery (ACM) ,1995
- Empirical failure analysis and validation of fault models in CMOS VLSI circuitsIEEE Design & Test of Computers, 1992
- E-PROOFS: A CMOS bridging fault simulatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Bridging and Stuck-At FaultsIEEE Transactions on Computers, 1974