I DDQ testing in CMOS digital ASICs
- 1 December 1992
- journal article
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 3 (4) , 317-325
- https://doi.org/10.1007/bf00135335
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- I/sub DDQ/ TESTING IN CMOS DIGITAL ASIC'S - PUTTING IT ALL TOGETHERPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test setsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Testing for parametric faults in static CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- CMOS bridging fault detectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Testing for Bridging Faults (Shorts) in CMOS CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983