An architectural level test generator for a hierarchical design environment

This publication has 17 references indexed in Scilit:

• ARTEST: AN ARCHITECTURAL LEVEL TEST GENERATOR FOR DATA PATH FAULTS AND CONTROL FAULTS
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Test generation for highly sequential circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• CONTEST: a concurrent test generator for sequential circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• High level test generation using data flow descriptions
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Sequential test generation at the register-transfer and logic levels
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Speed up of test generation using high-level primitives
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Hierarchical test generation using precomputed tests for modules
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
• Proofs
  Published by Association for Computing Machinery (ACM) ,1990
• A novel approach to accurate timing verification using RTL descriptions
  Published by Association for Computing Machinery (ACM) ,1989
• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
  IEEE Transactions on Computers, 1981