Modeling the effect of back gate bias on the subthreshold behavior of a SiGe-channel SOI PMOS device
- 31 December 1993
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 36 (12) , 1757-1761
- https://doi.org/10.1016/0038-1101(93)90223-d
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Transient behavior of subthreshold characteristics of fully depleted SOI MOSFETsIEEE Electron Device Letters, 1991
- Substrate bias dependence of subthreshold slopes in fully depleted silicon-on-insulator MOSFET'sIEEE Transactions on Electron Devices, 1991
- Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructuresIEEE Electron Device Letters, 1991
- High-performance fully depleted silicon-on-insulator transistorsIEEE Transactions on Electron Devices, 1990
- The characteristics of CMOS devices in oxygen-implanted silicon-on-insulator structuresIEEE Transactions on Electron Devices, 1988
- Silicon-germanium base heterojunction bipolar transistors by molecular beam epitaxyIEEE Electron Device Letters, 1988
- Indirect band gap of coherently strained bulk alloys on 〈001〉 silicon substratesPhysical Review B, 1985