Delay and bus current evaluation in CMOS logic circuits
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An accurate and fast analytical technique for computing the delay and the maximum supply current in a CMOS inverter is presented. It accounts for the effects of input slope, output load, transistor size, and short-circuit current. The accuracy is within 10% of the HSPICE level-3 model and the speed is more than three orders of magnitude faster than HSPICE. An extension of this technique is shown for the calculation of the delay and the maximum supply current of a chain of inverters, without recourse to integration. An efficient method for computing the total current waveform of the chain is also presented. The relative speed of computing the current waveform exceeds two orders of magnitude compared to HSPICE.Keywords
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