Exploiting the special structure of conflict and compatibility graphs in high-level synthesis
- 1 July 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (7) , 843-856
- https://doi.org/10.1109/43.293941
Abstract
No abstract availableThis publication has 17 references indexed in Scilit:
- Automatic synthesis of a multi-bus architecture for DSPPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Design process model in the Yorktown silicon compilerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A global optimization approach for architectural synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The combination of scheduling, allocation, and mapping in a single algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- SALSA: a new approach to scheduling with timing constraintsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Data path allocation based on bipartite weighted matchingPublished by Association for Computing Machinery (ACM) ,1990
- Synthesis using path-based schedulingPublished by Association for Computing Machinery (ACM) ,1990
- Force-directed scheduling for the behavioral synthesis of ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- REAL: a program for REgister ALlocationPublished by Association for Computing Machinery (ACM) ,1987