Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 30 (11) , 1183-1188
- https://doi.org/10.1109/4.475705
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- 1V high-speed digital circuit technology with 0.5μm multi-threshold CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 34 ns 256 Mb DRAM with boosted sense-ground schemePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Semiconductor technology crisis and challenges towards the year 2000Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Circuit design techniques for low-voltage operating and/or giga-scale DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM'sIEEE Journal of Solid-State Circuits, 1993
- A well-synchronized sensing/equalizing method for sub-1.0 V operating advanced DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- An experimental 1.5-V 64-Mb DRAMIEEE Journal of Solid-State Circuits, 1991
- A 1.5-V DRAM for battery-based applicationsIEEE Journal of Solid-State Circuits, 1989