A sub-nanosecond 0.5 μm 64 b adder design
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
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- A 200-MHz 64-b dual-issue CMOS microprocessorIEEE Journal of Solid-State Circuits, 1992
- High-Speed Binary AdderIBM Journal of Research and Development, 1981