Repeater insertion to reduce delay and power in RC tree structures

This publication has 9 references indexed in Scilit:

• Optimal methods of driving interconnections in VLSI circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFETs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Repeater design to reduce delay and power in resistive interconnect
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load
  Analog Integrated Circuits and Signal Processing, 1997
• A unified design methodology for CMOS tapered buffers
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
• Design of tapered buffers with local interconnect capacitance
  IEEE Journal of Solid-State Circuits, 1995
• Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
  IEEE Journal of Solid-State Circuits, 1990
• Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
  IEEE Journal of Solid-State Circuits, 1984
• Comments on "An optimized output stage for MOS integrated circuits" [with reply]
  IEEE Journal of Solid-State Circuits, 1975