Standby power reduction using dynamic voltage scaling and canary flip-flop structures

30 August 2004

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits

Vol. 39 (9) , 1504-1511
https://doi.org/10.1109/jssc.2004.831432

Abstract

Lowering V/sub DD/ during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13-/spl mu/m, dual-V/sub T/ test chip show that reducing V/sub DD/ to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage scaling for achieving savings near the optimum. This approach potentially provides over 2/spl times/ higher savings than an optimal open-loop approach without loss of state.

Keywords

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