Pleasure: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 530-537
https://doi.org/10.1109/dac.1983.1585704

Abstract

Programmable Logic Arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.

Keywords

This publication has 11 references indexed in Scilit:

An Algorithm for Optimal PLA Folding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982
PAOLA: A Tool for Topological Optimization of Large PLAs
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982
Techniques for Programmable Logic Array Folding
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982
Optimization of the PLA Area
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981
A Computer-Aided-Design System For Segmented-Folded PLA Macro-Cells
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981
Design of Large ALUs Using Multiple PLA Macros
IBM Journal of Research and Development, 1980
A High Density Programmable Logic Array Chip
IEEE Transactions on Computers, 1979
An associative logic matrix
IEEE Journal of Solid-State Circuits, 1976
An Introduction to Array Logic
IBM Journal of Research and Development, 1975
MINI: A Heuristic Approach for Logic Minimization
IBM Journal of Research and Development, 1974