Reconfiguration techniques for a single scan chain
- 1 June 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 14 (6) , 750-765
- https://doi.org/10.1109/43.387735
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- Optimal Seguencing of Scan RegistersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Selectable Length Partial Scan: A Method to Reduce Vector LengthPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Optimal configuring of multiple scan chainsIEEE Transactions on Computers, 1993
- Configuration of boundary scan chain for optimal testing of clusters of non boundary scan devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Reorganizing circuits to aid testabilityIEEE Design & Test of Computers, 1991
- The Ballast methodology for structured partial scan designIEEE Transactions on Computers, 1990
- Implementing macro test in silicon compiler designIEEE Design & Test of Computers, 1990
- Experience with ADAM synthesis systemPublished by Association for Computing Machinery (ACM) ,1989
- Optimal Sequencing of a Single Machine Subject to Precedence ConstraintsManagement Science, 1973