A design for testability scheme to reduce test application time in full scan
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults.Keywords
This publication has 7 references indexed in Scilit:
- Fast test generation for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An economical scan design for sequential logic test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CONTEST: a concurrent test generator for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test generation and verification for highly sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Test generation for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Logic Testing and Design for TestabilityPublished by MIT Press ,1985
- Fault Detection in Redundant CircuitsIEEE Transactions on Electronic Computers, 1967