MATEG: a hierarchical test generator for module-based circuits
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 491-494
- https://doi.org/10.1109/asic.1992.270215
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Hierarchical test generation using precomputed testsd for modulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A structured approach to macrocell testing using built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A hierarchical test generation methodology for digital circuitsJournal of Electronic Testing, 1990
- Testing Strategy and Technique for Macro-Based CircuitsIEEE Transactions on Computers, 1985
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- Hierarchical design methodologies and tools for VLSI chipsProceedings of the IEEE, 1983
- A Nine-Valued Circuit Model for Test GenerationIEEE Transactions on Computers, 1976