Hierarchical Test Program Development for Scan Testable Circuits
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 375
- https://doi.org/10.1109/test.1991.519697
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- A framework and method for hierarchical test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Symbolic test generation for hierarchically modeled digital systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Using hierarchy in macro cell test assemblyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- WSP-a processor for real-time wheel slip measurement in vehiclesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Hierarchical test assembly for macro based VLSI designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test generation for data-path logic: the F-path methodIEEE Journal of Solid-State Circuits, 1988
- A hierarchical approach test vector generationPublished by Association for Computing Machinery (ACM) ,1987
- Macro Testing: Unifying IC And Board TestIEEE Design & Test of Computers, 1986
- Functional Test Generation for Digital Circuits Described Using Binary Decision DiagramsIEEE Transactions on Computers, 1986
- Functional Level Primitives in Test GenerationIEEE Transactions on Computers, 1980