Monte Carlo simulation of deep-submicron SOI and conventional nMOSFET hot-electron-induced degradation

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Abstract
A coupled Monte Carlo/drift diffusion simulation is applied to an n-channel conventional bulk MOSFET and two fully depleted n-channel SOI transitors. It is found that the SOI devices are more sensitive to trapped electron charge. The models, however predict far fewer high energy electrons (and fewer generated electron-hole pairs), the net result being that the SOI devices are more resistant to hot-electron-induced degradation. Furthermore, the p/sup +/-polysilicon gate SOI devices with lower channel doping are less prone to hot-electron-induced degradation than their n/sup +/gate counterparts. It is shown that the hot-electron flux incident at the SiO/sub 2/ is a function of both the lateral field and the vertical oxide field, if one takes into account barrier lowering and/or tunneling into the oxide.