Comparison of DMOS/IGBT-compatible high-voltage termination structures and passivation techniques
- 1 January 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 40 (10) , 1845-1854
- https://doi.org/10.1109/16.277343
Abstract
No abstract availableKeywords
This publication has 17 references indexed in Scilit:
- Novel planar junction termination technique for high voltage power devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- High-voltage planar devices using field plate and semi-resistive layersIEEE Transactions on Electron Devices, 1991
- Vergleich verschiedener planarer Passivierungstechniken für HalbleiterleistungsbauelementeElectrical Engineering, 1989
- Interface effects of SIPOS passivationIEEE Transactions on Electron Devices, 1986
- High-voltage planar structure using SiO2-SIPOS-SiO2filmIEEE Electron Device Letters, 1985
- Characterisation and modelling of SIPOS on silicon high-voltage devicesIEE Proceedings I Solid State and Electron Devices, 1985
- Blocking capability of planar devices with field limiting ringsSolid-State Electronics, 1983
- High voltage thin layer devices (RESURF devices)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Highly reliable high-voltage transistors by use of the SIPOS processIEEE Transactions on Electron Devices, 1976
- Surface breakdown in silicon planar diodes equipped with field plateSolid-State Electronics, 1972