Computation of exact fault coverage for compact testing schemes
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1873-1876 vol.3
- https://doi.org/10.1109/iscas.1991.176772
Abstract
A strategy based on the use of intermediate signatures is developed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. A model is developed to predict fault simulation time, and used along with a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. A more sophisticated model which uses preliminary fault simulation results to make better estimations is also introduced. Simulation results for both models are presented demonstrating the feasibility of the strategy.<>Keywords
This publication has 5 references indexed in Scilit:
- FAST SIGNATURE COMPUTATION FOR LINEAR COMPACTORSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A fault simulation method based on stem regionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Computation of exact fault coverage for compact testing schemesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A Deductive Method for Simulating Faults in Logic CircuitsIEEE Transactions on Computers, 1972