A Testable PLA Design with Low Overhead and High Fault Coverage
- 1 August 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-33 (8) , 743-745
- https://doi.org/10.1109/TC.1984.5009362
Abstract
A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test.Keywords
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