Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 604-613
- https://doi.org/10.1109/test.1994.528005
Abstract
Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance degradation compared to 2- or 3-valued fault simulation.Keywords
This publication has 11 references indexed in Scilit:
- The parallel-test-detect fault simulation algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A three-valued fast fault simulator for scan-based VLSI-logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test pattern generation with restrictorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test generation and three-state elements, buses, and bidirectionalsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- ATPG for ultra-large structured designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- SOCRATES: a highly efficient automatic test pattern generation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Accelerated Fault Simulation and Fault Grading in Combinational CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Critical Path Tracing - An Alternative to Fault SimulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional TerminalsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsIEEE Transactions on Electronic Computers, 1967