Performance and V/sub dd/ scaling in deep submicrometer CMOS

This publication has 7 references indexed in Scilit:

• Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling
  IEEE Electron Device Letters, 1997
• Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
  IEEE Transactions on Electron Devices, 1997
• MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages
  Solid-State Electronics, 1996
• An accurate semi-empirical saturation drain current model for LDD n-MOSFET
  IEEE Electron Device Letters, 1996
• Device and Technology Impact on Low Power Electronics
  Published by Springer Nature ,1996
• CMOS scaling for high performance and low power-the next ten years
  Proceedings of the IEEE, 1995
• Minimizing power consumption in digital CMOS circuits
  Proceedings of the IEEE, 1995