Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 44 (11) , 1951-1957
- https://doi.org/10.1109/16.641365
Abstract
Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlightedKeywords
This publication has 11 references indexed in Scilit:
- Ultra-thin silicon dioxide leakage current and scaling limitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Interconnect scaling-the real limiter to high performance ULSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scalingIEEE Electron Device Letters, 1997
- Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effectsIEEE Transactions on Electron Devices, 1997
- MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltagesSolid-State Electronics, 1996
- An accurate semi-empirical saturation drain current model for LDD n-MOSFETIEEE Electron Device Letters, 1996
- Polysilicon gate depletion effect on IC performanceSolid-State Electronics, 1995
- Future CMOS scaling and reliabilityProceedings of the IEEE, 1993
- Approaches to ScalingPublished by Elsevier ,1989
- Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET'sIEEE Transactions on Electron Devices, 1986