Nano/CMOS architectures using a field-programmable nanowire interconnect

This publication has 18 references indexed in Scilit:

• Circuit Fabrication at 17 nm Half-Pitch by Nanoimprint Lithography
  Nano Letters, 2006
• Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes
  Nanotechnology, 2006
• Defect-tolerant interconnect to nanoelectronic circuits: internally redundant demultiplexers based on error-correcting codes
  Nanotechnology, 2005
• Scanned probe imaging of nanoscale conducting channels in Pt/alkanoic acid monolayer/Ti devices
  Applied Physics A, 2005
• Nanoscale molecular-switch crossbar circuits
  Nanotechnology, 2003
• Nanoscale molecular-switch devices fabricated by imprint lithography
  Applied Physics Letters, 2003
• Architecture and CAD for Deep-Submicron FPGAS
  Published by Springer Nature ,1999
• A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation
  IEEE Transactions on Electron Devices, 1998
• Performance optimization of VLSI interconnect layout
  Integration, 1996
• The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
  Journal of Applied Physics, 1948