Architectural level test generation for microprocessors
- 1 January 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (10) , 1288-1300
- https://doi.org/10.1109/43.317464
Abstract
Hierarchically designed microprocessor-like VLSI circuits have complex data paths and embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely difficult. After the instruction sequence is derived, to assign values at all interior lines without conflicts is also very difficult. In this paper, we propose a separation of test generation process into two phases: path analysis and value analysis. In the phase of path analysis, a new methodology for automatic assembly of a sequence of instructions is proposed to satisfy the internal test goals. In the phase of value analysis, an equation-solving algorithm is used to compute an exact value solution for all interior lines. This new ATPG methodology containing techniques for both path and value analysis forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on six high-level circuits. The results show that our approach is very effective in achieving complete automation for high-level test generationKeywords
This publication has 20 references indexed in Scilit:
- ARTEST: AN ARCHITECTURAL LEVEL TEST GENERATOR FOR DATA PATH FAULTS AND CONTROL FAULTSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Hierarchical test generation using precomputed testsd for modulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Beta: behavioral testability analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High level test generation using data flow descriptionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Speed up of test generation using high-level primitivesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An architectural level test generator based on nonlinear equation solvingJournal of Electronic Testing, 1993
- SOCRATES: a highly efficient automatic test pattern generation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- A hierarchical approach test vector generationPublished by Association for Computing Machinery (ACM) ,1987
- Functional Testing of MicroprocessorsIEEE Transactions on Computers, 1984
- Controllability/observability analysis of digital circuitsIEEE Transactions on Circuits and Systems, 1979