A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application
- 15 September 2009
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 17 (12) , 1742-1748
- https://doi.org/10.1109/TVLSI.2009.2017794
Abstract
An all-digital clock and data recovery (CDR) with a digital threshold decision updating technique for SFI-5 application is presented in this paper. The CDR updates its decision upon the phase error reaching a threshold value by examining the phase errors in the data bits within an examining window at the baud rate. High jitter tolerance performance is obtained and the phase acquisition can be achieved within one baud period. The proposed CDR is embodied with 900 transistors and the core CDR consumes 5 mW with 1.2 V supply at 2.5 Gb/s. Measured results verify the digital threshold decision technique and its low-complexity implementation for SFI-5 application.Keywords
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