CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 13.1/1-13.1/8
- https://doi.org/10.1109/cicc.1991.164091
Abstract
The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I/sub DDQ/ testing, is presented.Keywords
This publication has 17 references indexed in Scilit:
- Errors in testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- IC quality and test transparencyIEEE Transactions on Industrial Electronics, 1989
- Built-In Self-Test Trends in Motorola MicroprocessorsIEEE Design & Test of Computers, 1985
- Characterization and Testing of Physical Failures in MOS Logic CircuitsIEEE Design & Test of Computers, 1984
- The inadequacy of the stuck-at fault model for testing mos lsi circuits: a review of mos failure mechanisms and some implications for computer-aided design and test of mos lsi circuitsSoftware & Microsystems, 1984
- Defect Level as a Function of Fault CoverageIEEE Transactions on Computers, 1981
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978
- On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic NetsIEEE Transactions on Electronic Computers, 1966
- Techniques for the diagnosis of switching circuit failuresIEEE Transactions on Communication and Electronics, 1964