Effects of flash EEPROM floating gate morphology on electrical behavior of fast programming bits
- 1 July 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 46 (7) , 1355-1362
- https://doi.org/10.1109/16.772476
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devicesIEEE Transactions on Electron Devices, 1996
- A 5 V-compatible flash EEPROM cell with microsecond programming time for embedded memory applicationsIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1994
- Erratic Erase In ETOX/sup TM/ Flash Memory ArrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A novel cell structure suitable for a 3 volt operation, sector erase flash memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Polysilicon encapsulated local oxidationIEEE Electron Device Letters, 1991
- The role of electron trap creation in enhanced hot-carrier degradation during AC stress (n-channel MOSFET)IEEE Electron Device Letters, 1990
- A 90-ns one-million erase/program cycle 1-Mbit flash memoryIEEE Journal of Solid-State Circuits, 1989
- Corner-field induced drain leakage in thin oxide MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A reliable approach to charge-pumping measurements in MOS transistorsIEEE Transactions on Electron Devices, 1984
- Fowler-Nordheim Tunneling into Thermally Grown SiO2Journal of Applied Physics, 1969