On generating compact test sequences for synchronous sequential circuits
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 14 references indexed in Scilit:
- Compaction of ATPG-generated test sequences for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- FREEZE: a new approach for testing sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new test generation method for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test generation for synchronous sequential circuits based on fault extractionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sequential circuit test generation in a genetic algorithm frameworkPublished by Association for Computing Machinery (ACM) ,1994
- Classification of faults in synchronous sequential circuitsIEEE Transactions on Computers, 1993
- On achieving a complete fault coverage for sequential machines using the transition fault modelPublished by Association for Computing Machinery (ACM) ,1991
- A directed search method for test generation using a concurrent simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- SMART And FAST: Test Generation for VLSI Scan-Design CircuitsIEEE Design & Test of Computers, 1986